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FEATURES Fast Throughput Rate: 200 kSPS Specified for AVDD of 2.7 V to 5.25 V Low Power: 3.6 mW Max at 200 kSPS with 3 V Supply 7.5 mW Max at 200 kSPS with 5 V Supply 4 (Single-Ended) Inputs with Sequencer Wide Input Bandwidth: 70 dB Min SNR at 50 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPITM/QSPITM/ MICROWIRETM/DSP Compatible Shutdown Mode: 0.5 A Max 16-Lead TSSOP Package
4-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 16-Lead TSSOP AD7923
FUNCTIONAL BLOCK DIAGRAM
AVDD REFIN VIN0 * * * * * * * * * * * * * VIN3
T/H 12-BIT SUCCESSIVE APPROXIMATION ADC I/P MUX
SCLK DOUT SEQUENCER CONTROL LOGIC DIN CS
GENERAL DESCRIPTION
The AD7923 is a 12-bit, high speed, low power, 4-channel, successive approximation ADC. The part operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 200 kSPS. The part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 8 MHz. The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipeline delays associated with the part. The AD7923 uses advanced design techniques to achieve very low power dissipation at maximum throughput rates. At maximum throughput rates, the AD7923 consumes 1.2 mA maximum with 3 V supplies, and with 5 V supplies the current consumption is 1.5 mA maximum. Through the configuration of the Control Register, the analog input range for the part can be selected as 0 V to REFIN or 0 V to 2 REFIN, with either straight binary or twos complement output coding. The AD7923 features four single-ended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequentially. The conversion time for the AD7923 is determined by the SCLK frequency, as this is also used as the master clock to control the conversion. The conversion time may be as short as 800 ns with a 20 MHz SCLK.
AD7923
VDRIVE GND
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption. The AD7923 offers up to 200 kSPS throughput rates. At the maximum throughput rate with 3 V supplies, the AD7923 dissipates just 3.6 mW of power maximum. 2. Four Single-Ended Inputs with a Channel Sequencer. A consecutive sequence of channels, through which the ADC will cycle and convert on, can be selected. 3. Single-Supply Operation with VDRIVE Function. The AD7923 operates from a single 2.7 V to 5.25 V supply. The VDRIVE function allows the serial interface to connect directly to either 3 V or 5 V processor systems independent of AV DD. 4. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. The part also features various shutdown modes to maximize power efficiency at lower throughput rates. Current consumption is 0.5 mA maximum when in full shutdown. 5. No Pipeline Delay. The part features a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once off conversion control.
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AD7923-SPECIFICATIONS
Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD)2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY2 Resolution Integral Nonlinearity Differential Nonlinearity 0 V to REFIN Input Range Offset Error Offset Error Match Gain Error Gain Error Match 0 V to 2 REFIN Input Range Positive Gain Error Positive Gain Error Match Zero Code Error Zero Code Error Match Negative Gain Error Negative Gain Error Match ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance REFERENCE INPUT REFIN Input Voltage DC Leakage Current REFIN Input Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding
(AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.)
B Version1 70 69 70 -77 -73 -78 -76 -90 -90 10 50 -85 8.2 1.6 12 1 -0.9/+1.5 8 0.5 1.5 0.5 1.5 0.5 8 0.5 1 0.5 0 to REFIN 0 to 2 REFIN 1 20 2.5 1 36 0.7 VDRIVE 0.3 VDRIVE 1 10 Unit dB min dB min dB min dB max dB max dB max dB max dB typ dB typ ns typ ps typ dB typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max V V mA max pF typ V mA max kW typ V min V max mA max pF max Test Conditions/Comments fIN = 50 kHz Sine Wave, fSCLK = 20 MHz @5V @ 3 V Typically 70 dB @ 5 V Typically -84 dB @ 3 V Typically -77 dB @ 5 V Typically -86 dB @ 3 V Typically -80 dB fa = 40.1 kHz, fb = 41.5 kHz
fIN = 400 kHz @ 3 dB @ 0.1 dB
Guaranteed No Missed Codes to 12 Bits. Straight Binary Output Coding Typically 0.5 LSB
-REFIN to +REFIN Biased about REFIN with Twos Complement Output Coding Typically 0.8 LSB
RANGE Bit Set to 1 RANGE Bit Set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V
1% Specified Performance fSAMPLE = 200 kSPS
Typically 10 nA, VIN = 0 V or VDRIVE
VDRIVE - 0.2 V min 0.4 V max 1 mA max 10 pF max Straight (Natural) Binary Twos Complement
ISOURCE = 200 mA, AVDD = 2.7 V to 5.25 V ISINK = 200 mA Coding Bit Set to 1 Coding Bit Set to 0
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Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS AVDD VDRIVE IDD4 During Conversion Normal Mode (Static) Normal Mode (Operational) fSAMPLE = 200 kSPS Using Auto Shutdown Mode fSAMPLE = 200 kSPS Auto Shutdown (Static) Full Shutdown Mode Power Dissipation4 Normal Mode (Operational) fSAMPLE = 200 kSPS Auto Shutdown (Static) Full Shutdown Mode
NOTES 1 Temperature ranges as follows: B Version: -40C to +85C. 2 See Terminology section. 3 Sample tested @ 25C to ensure compliance. 4 See Power versus Throughput Rate section. Specifications subject to change without notice.
B Version1 800 300 300 200 2.7/5.25 2.7/5.25 2.7 2.0 600 1.5 1.2 900 650 0.5 0.5 7.5 3.6 2.5 1.5 2.5 1.5
Unit ns max ns max ns max kSPS max V min/max V min/max mA max mA max mA typ mA max mA max mA typ mA typ mA max mA max mW max mW max mW max mW max mW max mW max
Test Conditions/Comments 16 SCLK Cycles with SCLK at 20 MHz Sine Wave Input Full-Scale Step Input See Serial Interface Section
Digital I/Ps = 0 V or VDRIVE AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz AVDD = 2.7 V to 5.25 V, SCLK On or Off AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz AVDD = 4.75 V to 5.25 V, fSAMPLE = 200 kSPS AVDD = 2.7 V to 3.6 V, fSAMPLE = 200 kSPS SCLK On or Off (20 nA typ) SCLK On or Off (20 nA typ) AVDD = 5 V, fSCLK = 20 MHz AVDD = 3 V, fSCLK = 20 MHz AVDD = 5 V AVDD = 3 V AVDD = 5 V AVDD = 3 V
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AD7923 TIMING SPECIFICATIONS1
Parameter fSCLK
2
(AVDD = 2.7 V to 5.25 V, VDRIVE
AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.)
Limit at TMIN, TMAX AD7923 AVDD = 3 V 10 20 16 tSCLK 50 10 35 40 0.4 tSCLK 0.4 tSCLK 10 15/45 10 5 20 1 AVDD = 5 V 10 20 16 tSCLK 50 10 30 40 0.4 tSCLK 0.4 tSCLK 10 15/35 10 5 20 1 Unit kHz min MHz max ns min ns min ns max ns max ns min ns min ns min ns min/max ns min ns min ns min ms max Minimum Quiet Time Required between CS Rising Edge and Start of Next Conversion CS to SCLK Setup Time Delay from CS until DOUT Three-State Disabled Data Access Time after SCLK Falling Edge SCLK Low Pulsewidth SCLK High Pulsewidth SCLK to DOUT Valid Hold Time SCLK Falling Edge to DOUT High Impedance DIN Setup Time Prior to SCLK Falling Edge DIN Hold Time after SCLK Falling Edge Sixteenth SCLK Falling Edge to CS High Power-Up Time from Full Power-Down/Auto Shutdown Mode Description
tCONVERT tQUIET t2 t3 3 t4 3 t5 t6 t7 t8 4 t9 t10 t11 t12
NOTES 1 Sample tested at 25C to ensure compliance. All input signals are specified with t R = tF = 5 ns (10% to 90% of AV DD) and timed from a voltage level of 1.6 V. See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2 Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 VDRIVE. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, quoted in the timing characteristics t 8, is the true bus relinquish time of the part and is independent of the bus loading. Specifications subject to change without notice.
200 A
IOL
TO OUTPUT PIN
CL 50pF
1.6V
200 A
IOH
Figure 1. Load Circuit for Digital Output Timing Specifications
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ABSOLUTE MAXIMUM RATINGS 1
(TA = 25C, unless otherwise noted.)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VDRIVE to AGND . . . . . . . . . . . . . . . . -0.3 V to AVDD + 0.3 V Analog Input Voltage to AGND . . . . -0.3 V to AVDD + 0.3 V Digital Input Voltage to AGND . . . . . . . . . . . . -0.3 V to +7 V Digital Output Voltage to AGND . . . . -0.3 V to AVDD + 0.3 V REFIN to AGND . . . . . . . . . . . . . . . . -0.3 V to AVDD + 0.3 V Input Current to Any Pin Except Supplies2 . . . . . . . . 10 mA Operating Temperature Range Commercial (B Version) . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW qJA Thermal Impedance . . . . . . . . . . . . 150.4C/W (TSSOP) qJC Thermal Impedance . . . . . . . . . . . . . 27.6C/W (TSSOP) Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Model AD7923BRU EVAL-AD7923CB2 EVAL-CONTROL BRD23
Temperature Range -40C to +85C
Linearity Error (LSB)1 1
Package Option RU-16
Package Description TSSOP Evaluation Board Controller Board
NOTES 1 Linearity error here refers to integral linearity error. 2 This can be used as a standalone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes. 3 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, the you will need to order the particular ADC evaluation board, e.g., EVAL-AD7923CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the relevant Evaluation Board Application Note for more information.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7923 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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AD7923
PIN CONFIGURATION 16-Lead TSSOP
SCLK 1 DIN 2 CS 3 AGND 4 AVDD 5 AVDD 6 REFIN 7 AGND 8
16 15
AGND VDRIVE DOUT
AD7923
14
TOP VIEW 13 AGND (Not to Scale) 12 VIN0
11 10 9
VIN1 VIN2 VIN3
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2 3 4, 8, 13, 16
Mnemonic SCLK DIN CS AGND
Function Serial Clock. Logic Input. SCLK provides the serial clock for accessing data for the part. This clock input is also used as the clock source for the AD7923 conversion process. Data In. Logic Input. Data to be written to the AD7923 Control Register is provided on this input and is clocked into the register on the falling edge of SCLK (see the Control Register section). Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7923 and framing the serial data transfer. Analog Ground. Ground reference point for all analog circuitry on the AD7923. All analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected together. Analog Power Supply Input. The AVDD range for the AD7923 is from 2.7 V to 5.25 V. For the 0 V to 2 REFIN range, AVDD should be from 4.75 V to 5.25 V. Reference Input for the AD7923. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V 1% for specified performance. Analog Input 0 through Analog Input 3. Four single-ended analog input channels that are multiplexed into the on-chip track-and-hold. The analog input channel to be converted is selected by using the address bits ADD1 and ADD0 of the Control Register. The address bits in conjunction with the SEQ1 and SEQ0 bits allow the sequencer to be programmed. The input range for all input channels can extend from 0 V to REFIN or from 0 V to 2 REFIN as selected via the RANGE bit in the Control Register. Any unused input channels must be connected to AGND to avoid noise pickup. Data Out. Logic Output. The conversion result from the AD7923 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7923 consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, MSB first. The output coding may be selected as straight binary or twos complement via the CODING bit in the Control Register. Logic Power Supply Input. The voltage supplied at this pin determines at which voltage the serial interface of the AD7923 will operate.
5, 6 7 12-9
AVDD REFIN VIN0-VIN3
14
DOUT
15
VDRIVE
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TERMINOLOGY Integral Nonlinearity
This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero-scale, a point 1 LSB below the first code transition, and full-scale, a point 1 LSB above the last code transition.
Differential Nonlinearity
Negative Gain Error Match This is the difference in Negative Gain Error between any two channels.
Channel-to-Channel Isolation
This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
Offset Error
Channel-to-Channel Isolation is a measure of the level of crosstalk between channels. It is measured by applying a full-scale 400 kHz sine wave signal to all three nonselected input channels and determining how much that signal is attenuated in the selected channel with a 50 kHz signal. The figure is given worst-case across all four channels for the AD7923.
PSR (Power Supply Rejection)
This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
Variations in power supply will affect the full-scale transition, but not the converter's linearity. Power supply rejection is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. See Typical Performance Characteristics.
Track-and-Hold Acquisition Time
This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., REFIN - 1 LSB) after the offset error has been adjusted out.
Gain Error Match
This is the difference in Gain Error between any two channels.
Zero Code Error
The track-and-hold amplifier returns into track mode at the end of conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1 LSB, after the end of conversion.
Signal-to-(Noise + Distortion) Ratio
This applies when using the twos complement output coding option, in particular to the 2 REFIN input range with -REFIN to +REFIN biased about the REFIN point. It is the deviation of the midscale transition (all 0s to all 1s) from the ideal VIN voltage, i.e., REFIN - 1 LSB.
Zero Code Error Match
This is the difference in Zero Code Error between any two channels.
Positive Gain Error
This is the measured ratio of signal-to-(noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal-to-( Noise + Distortion) = (6.02N + 1.76 ) dB Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion (THD)
This applies when using the twos complement output coding option, in particular to the 2 REFIN input range with -REFIN to +REFIN biased about the REFIN point. It is the deviation of the last code transition (011. . .110) to (011 . . . 111) from the ideal (i.e., +REFIN - 1 LSB) after the Zero Code Error has been adjusted out.
Positive Gain Error Match
Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7923, it is defined as:
THD ( dB ) = 20 log
V22 + V32 + V42 + V52 + V62 V1
This is the difference in Positive Gain Error between any two channels.
Negative Gain Error
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics.
This applies when using the twos complement output coding option, in particular to the 2 REFIN input range with -REFIN to +REFIN biased about the REFIN point. It is the deviation of the first code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e., -REFIN + 1 LSB) after the Zero Code Error has been adjusted out.
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AD7923-Typical Performance Characteristics
PERFORMANCE CURVES
TPC 1 shows a typical FFT plot for the AD7923 at 200 kSPS sample rate and 50 kHz input frequency. TPC 2 shows the signal-to-(noise+distortion) ratio performance versus input frequency for various supply voltages while sampling at 200 kSPS with an SCLK of 20 MHz. TPC 3 shows the power supply rejection ratio versus supply ripple frequency for the AD7923 with no decoupling. The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency f, to the power of a 200 mV p-p sine wave applied to the ADC AVDD supply of frequency fS:
PSRR( dB ) = 10 log( Pf /Pf s )
TPC 4 shows a graph of total harmonic distortion versus analog input frequency for various supply voltages, while TPC 5 shows a graph of total harmonic distortion versus analog input frequency for various source impedances. See the Analog Input section. TPC 6 and TPC 7 show typical INL and DNL plots for the AD7923.
0 -10 -20 -30 AVDD = 5V, 200mV p-p SINE WAVE ON AVDD REFIN = 2.5V, 1 F CAPACITOR TA = 25 C
Pf is equal to the power at frequency f in ADC output; PfS is equal to the power at frequency fS coupled onto the ADC AVDD supply. Here a 200 mV p-p sine wave is coupled onto the AVDD supply.
-10 4096 POINT FFT AVDD = 4.75V fSAMPLE = 200kSPS fIN = 50kHz SINAD = 70.714dB THD = -82.853dB SFDR = -84.815dB
PSRR - dB
-40 -50 -60 -70 -80 -90
-30
0
20
40
60 80 100 120 140 160 SUPPLY RIPPLE FREQUENCY - kHz
180
200
SNR - dB
-50
TPC 3. PSRR vs. Supply Ripple Frequency
-50 -55
-70
fSAMPLE = 200kSPS TA = 25 C RANGE = 0V TO REFIN
-90
-60 -65 0 10 20 30 40 60 50 70 FREQUENCY - kHz 80 90 100
THD - dB
-110
-70 AVDD = V DRIVE = 2.7V -75 -80 -85 AVDD = V DRIVE = 3.6V
TPC 1. Dynamic Performance at 200 kSPS
75
AVDD = V DRIVE = 5.25V AVDD = V DRIVE = 4.75V 70
SINAD - dB
-90 10
AVDD = V DRIVE = 4.75V AVDD = V DRIVE = 5.25V 100 INPUT FREQUENCY - kHz
AVDD = V DRIVE = 3.6V AVDD = V DRIVE = 2.7V
TPC 4. THD vs. Analog Input Frequency for Various Supply Voltages at 200 kSPS
-55
65
fSAMPLE = 200kSPS
fSAMPLE = 200kSPS
TA = 25 C RANGE = 0 V TO REFIN 60 0 INPUT FREQUENCY - kHz 100
THD - dB
-60 -65 -70
TA = 25 C AVDD = 5.25V RANGE = 0V TO REFIN
RIN = 1000
TPC 2. SINAD vs. Analog Input Frequency for Various Supply Voltages at 200 kSPS
-75 -80
RIN = 100 RIN = 10
-85 -90
RIN = 50
-95 10 INPUT FREQUENCY - kHz
100
TPC 5. THD vs. Analog Input Frequency for Various Source Impedances
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1.0 0.8 0.6
DNL ERROR - LSB
1.0
AVDD = V DRIVE = 5V TEMP = 25 C
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
AVDD = V DRIVE = 5V TEMP = 25 C
INL ERROR - LSB
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 CODE 3072 3584 4096
-1.0
0
512
1024
1536
2048 2560 CODE
3072
3584
4096
TPC 6. Typical INL
TPC 7. Typical DNL
CONTROL REGISTER
The Control Register on the AD7923 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7923 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data transferred on the DIN line corresponds to the AD7923 configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 12 falling clock edges (after CS falling edge) is loaded to the Control Register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table I.
Table I. Control Register Bit Functions
MSB WRITE Bit 11 SEQ1 DONTC DONTC Comment ADD1 ADD0 PM1 PM0 SEQ0 DONTC RANGE
LSB CODING
Mnemonic WRITE
The value written to this bit of the Control Register determines whether the following 11 bits will be loaded to the Control Register. If this bit is a 1, the following 11 bits will be written to the Control Register; if it is a 0, the remaining 11 bits are not loaded to the Control Register and it remains unchanged. The SEQ1 bit in the Control Register is used in conjunction with the SEQ0 bit to control the use of the sequencer function. (See Table IV.) Don't Care
10 9-8 7-6
SEQ1 DONTC
ADD1, ADD0 These two address bits are loaded at the end of the present conversion and select which analog input channel is to be converted in the next serial transfer, or they may select the final channel in a consecutive sequence as described in Table IV. The selected input channel is decoded as shown in Table II. The address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of data. (See the Serial Interface section.) The next channel to be converted on will be selected by the mux on the 14th SCLK falling edge. PM1, PM0 SEQ0 DONTC RANGE Power Management Bits. These two bits decode the mode of operation of the AD7923 as shown in Table III. The SEQ0 bit in the Control Register is used in conjunction with the SEQ1 bit to control the use of the sequencer function. (See Table IV.) Don't Care This bit selects the analog input range to be used on the AD7923. If it is set to 0, the analog input range will extend from 0 V to 2 REFIN. If it is set to 1, the analog input range will extend from 0 V to REFIN (for the next conversion). For the 0 V to 2 REFIN range, AVDD = 4.75 V to 5.25 V. This bit selects the type of output coding the AD7923 will use for the conversion result. If this bit is set to 0, the output coding for the part will be twos complement. If this bit is set to 1, the output coding from the part will be straight binary (for the next conversion).
5, 4 3 2 1
0
CODING
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Table II. Channel Selection
ADD1 0 0 1 1
ADD0 0 1 0 1
Analog Input Channel VIN0 VIN1 VIN2 VIN3
Table III. Power Mode Selection
PM1 PM0 Mode 1 1 1 0 Normal Operation. In this mode, the AD7923 remains in full power mode, regardless of the status of any of the logic inputs. This mode allows the fastest possible throughput rate from the AD7923. Full Shutdown. In this mode, the AD7923 is in full shutdown mode with all circuitry on the AD7923 powering down. The AD7923 retains the information in the Control Register while in full shutdown. The part remains in full shutdown until these bits are changed. Auto Shutdown. In this mode, the AD7923 automatically enters full shutdown mode at the end of each conversion when the Control Register is updated. Wake-up time from full shutdown is 1 ms, and the user should ensure that 1 ms has elapsed before attempting to perform a valid conversion on the part in this mode. Invalid Selection. This configuration is not allowed.
0
1
0
0
SEQUENCER OPERATION
The configuration of the SEQ1 and SEQ0 bits in the Control Register allows the user to select a particular mode of operation of the sequencer function. Table IV outlines the three modes of operation of the sequencer.
Table IV. Sequence Selection
SEQ1 SEQ0 Sequence Type 0 X This configuration means that the sequence function is not used. The analog input channel selected for each individual conversion is determined by the contents of the channel address bits ADD1, ADD0 in each prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer function being used, where each write to the AD7923 selects the next channel for conversion. (See Figure 2.) If the SEQ1 and SEQ0 bits are set in this way, the sequence function will not be interrupted upon completion of the WRITE operation. This allows other bits in the Control Register to be altered between conversions while in a sequence without terminating the cycle. This configuration is used in conjunction with the channel address bits ADD1, ADD0 to program continuous conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the channel address bits in the Control Register. (See Figure 3.)
1
0
1
1
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Figure 2 reflects the traditional operation of a multichannel ADC, where each serial transfer selects the next channel for conversion. In this mode of operation the Sequencer function is not used. Figure 3 shows how to program the AD7923 to continuously convert on a sequence of consecutive channels from Channel 0 to a selected final channel. To exit this mode of operation and revert back to the traditional mode of operation of a multichannel ADC (as outlined in Figure 2), ensure that the WRITE bit = 1 and SEQ1 = SEQ0 = 0 on the next serial transfer.
POWER-ON
CIRCUIT INFORMATION
The AD7923 is high speed, 4-channel, 12-bit, single-supply A/D converter. The part can be operated from a 2.7 V to 5.25 V supply. When operated from either a 5 V or 3 V supply, the AD7923 is capable of throughput rates of 200 kSPS. The conversion time may be as short as 800 ns when provided with a 20 MHz clock. The AD7923 provides the user with an on-chip, track-and-hold A/D converter, and with a serial interface housed in a 16-lead TSSOP package. The AD7923 has four single-ended input channels with a channel sequencer, allowing the user to select a channel sequence through which the ADC can cycle with each consecutive CS falling edge. The serial clock input accesses data from the part, controls the transfer of data written to the ADC, and provides the clock source for the successive approximation A/D converter. The analog input range for the AD7923 is 0 V to REFIN or 0 V to 2 REFIN, depending on the status of Bit 1 in the Control Register. For the 0 to 2 REFIN range, the part must be operated from a 4.75 V to 5.25 V supply. The AD7923 provides flexible power management options to allow the user to achieve the best power performance for a given throughput rate. These options are selected by programming the Power Management bits, PM1 and PM0, in the Control Register.
DUMMY CONVERSION
CS
DIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. SELECT CHANNEL A1, A0 FOR CONVERSION. SEQ1 = 0, SEQ0 = x
DOUT: CONVERSION RESULT FROM PREVIOUSLY SELECTED CHANNEL A1, A0
CS
DIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. SELECT A1, A0 FOR CONVERSION. SEQ1 = 0, SEQ0 = x
WRITE BIT = 1, SEQ1 = 0, SEQ0 = x
CONVERTER OPERATION
Figure 2. SEQ1 Bit = 0, SEQ0 Bit = x Flowchart
POWER-ON
DUMMY CONVERSION
CS
DIN: WRITE TO CONTROL REGISTER, WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. SELECT CHANNEL A1, A0 FOR CONVERSION. SEQ1 = 1, SEQ0 = 1
The AD7923 is a 12-bit successive approximation analog-todigital converter based around a capacitive DAC. The AD7923 can convert analog input signals in the range 0 V to REFIN or 0 V to 2 REFIN. Figures 4 and 5 show simplified schematics of the ADC. The ADC is comprised of Control Logic, SAR, and a capacitive DAC, which are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. Figure 4 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on the selected VIN channel.
CAPACITIVE DAC
DOUT: CONVERSION RESULT FROM CHANNEL 0
VIN0
WRITE BIT = 0
A SW1 B
4k SW2 COMPARATOR CONTROL LOGIC
CS
CONTINUOUSLY CONVERTS ON A CONSECUTIVE SEQUENCE OF CHANNELS FROM CHANNEL 0 UP TO AND INCLUDING THE PREVIOUSLY SELECTED A1, A0 IN THE CONTROL REGISTER
VIN3 AGND
Figure 4. ADC Acquisition Phase
CONTINUOUSLY CONVERTS ON THE SELECTED SEQUENCE OF CHANNELS BUT WILL ALLOW RANGE, CODING, ETC., TO CHANGE IN THE CONTROL REGISTER WITHOUT INTERRUPTING THE SEQUENCE, PROVIDED SEQ = 1, SEQ0 = 0
CS
WRITE BIT = 1, SEQ1 = 1, SEQ0 = 0
Figure 3. SEQ1 Bit = 1, SEQ0 Bit = 1 Flowchart
REV. 0
-11-
AD7923
When the ADC starts a conversion (see Figure 5), SW2 will open and SW1 will move to position B, causing the comparator to become unbalanced. The Control Logic and the capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The Control Logic generates the ADC output code. Figures 7 and 8 show the ADC transfer functions.
CAPACITIVE DAC
ADC TRANSFER FUNCTION
The output coding of the AD7923 is either straight binary or twos complement, depending on the status of the LSB in the Control Register. The designed code transitions occur at successive LSB values (i.e., 1 LSB, 2 LSBs, and so on). The LSB size is REFIN/4096 for the AD7923. The ideal transfer characteristic for the AD7923 when straight binary coding is selected is shown in Figure 7, and the ideal transfer characteristic for the AD7923 when twos complement coding is selected is shown in Figure 8.
B
SW2 COMPARATOR
VIN3 AGND
ADC CODE
VIN0 . .
A SW1
4k CONTROL LOGIC
Figure 5. ADC Conversion Phase
Analog Input
111...111 111...110 * * 111...000 * 011...111 * * 000...010 000...001 000...000 0V 1 LSB
1LSB
VREF/4096
Figure 6 shows an equivalent circuit of the analog input structure of the AD7923. The two diodes D1 and D2 provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mV. This will cause these diodes to become forward-biased and start conducting current into the substrate. 10 mA is the maximum current these diodes can conduct without causing irreversible damage to the part. Capacitor C1 in Figure 6 is typically about 4 pF and can primarily be attributed to pin capacitance. The resistor R1 is a lumped component made up of the on resistance of the track-and-hold switch and also includes the on resistance of the input multiplexer. The total resistance is typically about 400 W. Capacitor C2 is the ADC sampling capacitor and has a capacitance of 30 pF typically. For ac applications, removing high frequency components from the analog input signal is recommended by using an RC low-pass filter on the relevant analog input pin. In applications where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp will be a function of the particular application. When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance will depend on the amount of total harmonic distortion (THD) that can be tolerated. The THD will increase as the source impedance increases and performance will degrade. (See TPC 5.)
AVDD
+VREF ANALOG INPUT REFIN
1 LSB
NOTE: V REF IS EITHER REFIN OR 2
Figure 7. Straight Binary Transfer Characteristic
011...111 011...110 * * 000...001 000...000 111...111 * * 100...010 100...001 100...000 -VREF
ADC CODE
1LSB
2
VREF 4096
1LSB +VREF 1LSB VREF 1LSB ANALOG INPUT
Figure 8. Twos Complement Transfer Characteristic with REFIN REFIN Input Range
Figure 9 shows how useful the combination of the 2 REFIN input range and the twos complement output coding scheme is for handling bipolar input signals. If the bipolar input signal is biased about REFIN and twos complement output coding is selected, then REFIN becomes the zero code point, -REFIN is negative full scale, and +REFIN becomes positive full scale, with a dynamic range of 2 REFIN.
TYPICAL CONNECTION DIAGRAM
Handling Bipolar Input Signals
D1 R1 VIN C1 4pF D2
C2 30pF
CONVERSION PHASE: SWITCH OPEN TRACK PHASE: SWITCH CLOSED
Figure 6. Equivalent Analog Input Circuit
Figure 10 shows a typical connection diagram for the AD7923. In this setup the AGND pin is connected to the analog ground plane of the system. In Figure 10, REFIN is connected to a decoupled 2.5 V supply from a reference source, the AD780, to provide an analog input range of 0 V to 2.5 V (if RANGE bit is 1) or 0 V to 5 V (if RANGE bit is 0). Although the AD7923 is connected to a VDD of 5 V, the serial interface is connected to a 3 V microprocessor. The VDRIVE pin of the AD7923 is connected to the same 3 V supply of the microprocessor to allow a 3 V logic interface (see the Digital Inputs section). The conversion result is output in a 16-bit word. This 16-bit data stream consists of two leading zeros,
-12-
REV. 0
AD7923
VREF VDD 0.1 F REFIN AVDD VDRIVE R4 V R3 0V V R2 VIN0 * * VIN3 R3 R4 REFIN (= 0V) 100...000 DOUT +REFIN (= 2 REFIN) 011...111 VDD
AD7923
TWOS COMPLEMENT
DSP/ P
R1 R1 R2
000...000
-REFIN
Figure 9. Handling Bipolar Signals
two address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data. For applications where power consumption is of concern, the powerdown modes should be used between conversions or bursts of several conversions to improve power performance. See the Modes of Operation section.
0.1 F 10 F 5V SUPPLY SERIAL INTERFACE
0V TO REFIN
VIN 0 * * VIN3 AGND
AVDD
SCLK
AD7923
REFIN
DOUT CS VDRIVE DIN
C/ P
It is not necessary to write to the Control Register again once a sequencer operation has been initiated. The WRITE bit must be set to zero or the DIN line tied low to ensure that the Control Register is not accidently overwritten, or the sequence operation interrupted. If the Control Register is written to at any time during the sequence, the user must ensure that the SEQ1 and SEQ0 bits are set to 1,0 to avoid interrupting the automatic conversion sequence. This pattern will continue until the AD7923 is written to and the SEQ1 and SEQ0 bits are configured with any bit combination except 1,0 resulting in the termination of the sequence. If uninterrupted, however (WRITE bit = 0, or WRITE bit = 1 and SEQ1 and SEQ0 bits are set to 1,0), then upon completion of the sequence, the AD7923 sequencer will return to the Channel 0 and commence the sequence again. Regardless of which channel selection method is used, the 16-bit word output from the AD7923 during each conversion will always contain two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 12-bit conversion result. (See the Serial Interface section.)
Digital Inputs
0.1 F
2.5V
0.1 F
10 F 3V SUPPLY
AD780
NOTE: ALL UNUSED INPUT CHANNELS MUST BE CONNECTED TO AGND
Figure 10. Typical Connection Diagram
Analog Input Selection
Any one of four analog input channels may be selected for conversion by programming the multiplexer with the address bits ADD1 and ADD0 in the Control Register. The channel configurations are shown in Table II. The AD7923 may also be configured to automatically cycle through a number of channels as selected. The sequencer feature is accessed via the SEQ1 and SEQ0 bits in the Control Register. (See Table IV). The AD7923 can be programmed to continuously convert on a number of consecutive channels in ascending order from Channel 0 to a selected final channel as determined by the channel address bits ADD1 and ADD0. This is possible if the SEQ1 and SEQ0 bits are set to 1,1. The next serial transfer will then act on the sequence programmed by executing a conversion on Channel 0. The next serial transfer will result in a conversion on Channel 1, and so on, until the channel selected via the address bits ADD1, ADD0 is reached.
The digital inputs applied to the AD7923 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the AVDD + 0.3 V limit as on the analog inputs. Another advantage of SCLK, DIN, and CS not being restricted by the AVDD + 0.3 V limit is that possible power supply sequencing issues are avoided. If CS, DIN, or SCLK is applied before AVDD, there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V was applied prior to AVDD.
VDRIVE
The AD7923 also has the VDRIVE feature. VDRIVE controls the voltage at which the serial interface operates. VDRIVE allows the ADC to easily interface to both 3 V and 5 V processors. For example, if the AD7923 were operated with an AVDD of 5 V, the VDRIVE pin could be powered from a 3 V supply. The AD7923 has a larger dynamic range with an AVDD of 5 V while still being able to interface to 3 V processors. Care should be taken to ensure that VDRIVE does not exceed AVDD by more than 0.3 V. (See the Absolute Maximum Ratings section.)
REV. 0
-13-
AD7923
Reference
CS 1 12 16
An external reference source should be used to supply the 2.5 V reference to the AD7923. Errors in the reference source will result in gain errors in the AD7923 transfer function and will add to the specified full-scale errors of the part. A capacitor of at least 0.1 mF should be placed on the REFIN pin. Suitable reference sources for the AD7923 include the AD780, REF 193, and the AD1582. If 2.5 V is applied to the REFIN pin, the analog input range can be either 0 V to 2.5 V or 0 V to 5 V, depending on the setting of the RANGE bit in the Control Register.
MODES OF OPERATION
SCLK
DOUT
2 LEADING ZEROS + 2 CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DIN
DATA IN TO CONTROL REGISTER
NOTE: CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES
Figure 11. Normal Mode Operation
Full Shutdown (PM1 = 1, PM0 = 0)
The AD7923 has a number of different modes of operation, which are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. The mode of operation of the AD7923 is controlled by the power management bits, PM1 and PM0, in the Control Register, as detailed in Table III. When power supplies are first applied to the AD7923, care should be taken to ensure that the part is placed in the required mode of operation. (See the Powering Up the AD7923 section.)
Normal Mode (PM1 = PM0 = 1)
In this mode, all internal circuitry on the AD7923 is powered down. The part retains information in the Control Register during full shutdown. The AD7923 remains in full shutdown until the power management bits in the Control Register, PM1 and PM0, are changed. If a write to the Control Register occurs while the part is in Full Shutdown, with the power management bits changed to PM0 = PM1 = 1, Normal Mode, the part will begin to power up on the CS rising edge. The track-and-hold that was in hold while the part was in full shutdown will return to track on the 14th SCLK falling edge. A full 16-SCLK transfer must occur to ensure that the Control Register contents are updated; however, the DOUT line will not be driven during this wake-up transfer. To ensure that the part is fully powered up, tPOWER UP (t12) should have elapsed before the next CS falling edge; otherwise invalid data will be read if a conversion is initiated before this time. Figure 12 shows the general diagram for this sequence.
Auto Shutdown (PM1 = 0, PM0 = 1)
This mode is intended for the fastest throughput rate performance as the user does not have to worry about any power-up times with the AD7923 remaining fully powered at all time. Figure 11 shows the general diagram of the operation of the AD7923 in this mode. The conversion is initiated on the falling edge of CS and the track-and-hold will enter hold mode as described in the Serial Interface section. The data presented to the AD7923 on the DIN line during the first twelve clock cycles of the data transfer is loaded into the Control Register (provided WRITE bit is set to 1). The part will remain fully powered up in Normal Mode at the end of the conversion as long as PM1 and PM0 are set to 1 in the write transfer during that same conversion. To ensure continued operation in Normal Mode, PM1 and PM0 must both be loaded with 1 on every data transfer, assuming a write operation is taking place. If the WRITE bit is set to 0, the power management bits will be left unchanged and the part will remain in Normal Mode. Sixteen serial clock cycles are required to complete the conversion and access the conversion result. The track-and-hold will go back into track on the 14th SCLK falling edge. CS may then idle high until the next conversion or may idle low until sometime prior to the next conversion (effectively idling CS low). For specified performance, the throughput rate should not exceed 200 kSPS, which means there should be no less than 5 ms between consecutive falling edges of CS when converting. The actual frequency of the SCLK used will determine the duration of the conversion within this 5 ms cycle; however, once a conversion is complete, and CS has returned high, a minimum of the quiet time, tQUIET, must elapse before bringing CS low again to initiate another conversion.
In this mode, the AD7923 automatically enters shutdown at the end of each conversion when the Control Register is updated. When the part is in shutdown, the track-and-hold is in Hold Mode. Figure 13 shows the general diagram of the operation of the AD7923 in this mode. In Shutdown Mode all internal circuitry on the AD7923 is powered down. The part retains information in the Control Register during shutdown. The AD7923 remains in shutdown until the next CS falling edge it receives. On this CS falling edge, the track-and-hold that was in hold while the part was in shutdown will return to track. Wake-up time from Auto Shutdown is 1 ms maximum, and the user should ensure that 1 ms has elapsed before attempting a valid conversion. When running the AD7923 with a 20 MHz clock, one dummy 16 SCLK transfer should be sufficient to ensure that the part is fully powered up. During this dummy transfer, the contents of the Control Register should remain unchanged, therefore the WRITE bit should be 0 on the DIN line. Depending on the SCLK frequency used, this dummy transfer may affect the achievable throughput rate of the part, with every other data transfer being a valid conversion result. If, for example, the maximum SCLK frequency of 20 MHz was used, the Auto Shutdown Mode could be used at the full throughout rate of 200 kSPS without affecting the throughput rate at all. Only a portion of the cycle time is taken up by the conversion time and the dummy transfer for wake-up. In this mode, the power consumption of the part is greatly reduced with the part entering Shutdown at the end of each conversion. When the Control Register is programmed to move into Auto Shutdown, it does so at the end of the conversion. The user can move the ADC in and out of the low power state by controlling the CS signal. REV. 0
-14-
AD7923
PART IS IN FULL SHUTDOWN PART BEGINS TO POWER UP ON CS RISING EDGE AS PM1 = PM0 = 1 THE PART IS FULLY POWERED UP ONCE tPOWER UP HAS ELAPSED
t12
CS
1 14 16 1 14 16
SCLK
DOUT
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DIN
DATA IN TO CONTROL REGISTER CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. PM1 = 1, PM0 = 1
DATA IN TO CONTROL REGISTER TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 1 IN CONTROL REGISTER
Figure 12. Full Shutdown Mode Operation
PART ENTERS SHUTDOWN ON CS RISING EDGE AS PM1 0, PM0 1 CS 1 12 16 1 PART BEGINS TO POWER UP ON CS FALLING EDGE PART ENTERS SHUTDOWN ON CS RISING EDGE AS PM1 0, PM0 1
PART IS FULLY POWERED UP
DUMMY CONVERSION 12 16 1 12 16
SCLK
DOUT
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DIN
DATA IN TO CONTROL REGISTER CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS, PM1 0, PM0 1 CONTROL REGISTER CONTENTS SHOULD NOT CHANGE, WRITE BIT 0
DATA IN TO CONTROL REGISTER TO KEEP PART IN THIS MODE, LOAD PM1 0, PM0 IN CONTROL REGISTER OR SET WRITE BIT = 0 1
Figure 13. Auto Shutdown Mode Operation
Powering Up the AD7923
When supplies are first applied to the AD7923, the ADC may power up in any of the operating modes of the part. To ensure that the part is placed into the required operating mode, the user should perform a dummy cycle operation as outlined in Figures 14a through 14c. The dummy conversion operation must be performed to place the part into the desired mode of operation. To ensure that the part is in Normal Mode, this dummy cycle operation can be performed with the DIN line tied high, i.e., PM1, PM0 = 1,1 (depending on other required settings in the control register), but the minimum power-up time of 1 ms must be allowed from the rising edge of CS, where the Control Register is updated, before attempting the first valid conversion. This is to allow for the possibility that the part initially powered up in shutdown. If the desired mode of operation is Full Shutdown, then again only one dummy cycle is required after supplies are applied. In this dummy cycle, the user simply sets the power management bits,
PM1, PM0 = 1,0, and upon the rising edge of CS at the end of that serial transfer, the part will enter Full Shutdown. If the desired mode of operation is Auto Shutdown after supplies are applied, two dummy cycles will be required, the first with DIN tied high and the second dummy cycle to set the power management bits PM1 and PM0 = 0,1. On the second CS rising edge after the supplies are applied, the Control Register will contain the correct information and the part will enter Auto Shutdown Mode as programmed. If power consumption is of critical concern, then in the first dummy cycle the user may set PM1, PM0 = 1,0, i.e., Full Shutdown, and then place the part into Auto Shutdown in the second dummy cycle. For illustration purposes, Figure 14c is shown with DIN tied high on the first dummy cycle in this case. Figures 14a, 14b, and 14c each show the required dummy cycle(s) after supplies are applied in the case of Normal Mode, Full Shutdown Mode, and Auto Shutdown Mode, respectively, being the desired mode of operation.
REV. 0
-15-
AD7923
PART IS IN UNKNOWN MODE AFTER POWER-ON IF IN SHUTDOWN AT POWER-ON, PART BEGINS TO POWER UP ON CS RISING EDGE AS PM1 = PM0 = 1 ALLOW tPOWER TO ELAPSE
t12
CS 1 SCLK 14 16 1 14 16
DOUT
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DIN DIN LINE HIGH FOR FIRST DUMMY CONVERSION
DATA IN TO CONTROL REGISTER TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 1 IN CONTROL REGISTER
Figure 14a. Placing AD7923 into Normal Mode after Supplies are First Applied
PART IS IN UNKNOWN MODE AFTER POWER-ON PART ENTERS SHUTDOWN ON CS RISING EDGE AS PM1 = PM0 = 0
CS 1 SCLK 14 16
DOUT
INVALID DATA
DIN
DATA IN TO CONTROL REGISTER CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. PM1 = 1, PM0 = 0
Figure 14b. Placing AD7923 into Full Shutdown Mode after Supplies are First Applied
PART IS IN UNKNOWN MODE AFTER POWER-ON PART ENTERS AUTO SHUTDOWN ON CS RISING EDGE AS PM1 = 0, PM0 = 1
CS 1 SCLK 14 16 1 14 16
DOUT
INVALID DATA
INVALID DATA
DIN DIN LINE HIGH FOR FIRST DUMMY CONVERSION
DATA IN TO CONTROL REGISTER CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. PM1 = 0, PM0 = 1
Figure 14c. Placing AD7923 into Auto Shutdown Mode after Supplies are First Applied
POWER VERSUS THROUGHPUT RATE
In Auto Shutdown Mode, the average power consumption of the ADC may be reduced at any given throughput rate. The power saving will depend on the SCLK frequency used, i.e., conversion time. In some cases where the conversion time is a large proportion of the cycle time, the throughput rate would need to be reduced to take advantage of the power-down modes. Assuming a 20 MHz SCLK is used, the conversion time is 800 ns,
but the cycle time is 5 ms when the sampling rate is at a maximum of 200 kSPS. If the AD7923 is placed into shutdown for the remainder of the cycle time, then on average far less power will be consumed in every cycle compared to leaving the device in Normal Mode. Furthermore, Figure 15 shows how, as the throughput rate is reduced, the part remains in its shutdown longer and the average power consumption drops accordingly over time.
-16-
REV. 0
AD7923
For example, if the AD7923 is operated in a continuous sampling mode, with a throughput rate of 200 kSPS and an SCLK of 20 MHz (AVDD = 5 V), and the device is placed in Auto Shutdown Mode, i.e., if PM1 = 0 and PM0 = 1, then the power consumption is calculated as follows: The maximum power dissipation during conversion is 13.5 mW (IDD = 2.7 mA max, AVDD = 5 V). If the power-up time from Auto Shutdown is one dummy cycle, i.e., 1 ms, and the remaining conversion time is another cycle, i.e., 800 ns, then the AD7923 can be said to dissipate 13.5 mW for 1.8 ms during each conversion cycle. For the remainder of the conversion cycle, 3.2 ms, the part remains in Shutdown. The AD7923 can be said to dissipate 2.5 mW for the remaining 3.2 ms of the conversion cycle. If the throughput rate is 200 kSPS, the cycle time is 5 ms and the average power dissipated during each cycle is (1.8/5) (13.5 mW) + (3.2/5) (2.5 mW) = 4.8616 mW. Figure 15 shows the maximum power versus throughput rate when using the Auto Shutdown Mode with 5 V and 3 V supplies.
10
SERIAL INTERFACE
Figures 16 shows the detailed timing diagrams for serial interfacing to the AD7923. The serial clock provides the conversion clock and controls the transfer of information to and from the AD7923 during each conversion. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into hold mode, takes the bus out of three-state, and the analog input is sampled at this point. The conversion is also initiated at this point and will require 16 SCLK cycles to complete. The track-and-hold will go back into track on the 14th SCLK falling edge as shown in Figure 16 at Point B. On the 16th SCLK falling edge the DOUT line will go back into three-state. If the rising edge of CS occurs before 16 SCLKs have elapsed, the conversion will be terminated and the DOUT line will go back into three-state and the Control Register will not be updated; otherwise DOUT returns to three-state on the 16th SCLK falling edge, as shown in Figure 16. Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7923. For the AD7923, the twelve bits of data are preceded by two leading zeros and two channel address bits ADD1 and ADD0, identifying which channel the result corresponds to. CS going low clocks out the first leading zero to be read in by the microcontroller or DSP on the first falling edge of SCLK. The first falling edge of SCLK will also clock out the second leading zero to be read in by the microcontroller or DSP on the second SCLK falling edge, and so on. The remaining two address bits and 12-data bits are then clocked out by subsequent SCLK falling edges beginning with the first address bit ADD1, thus the second falling clock edge on the serial clock has the second leading zero provided and also clocks out address bit ADD1. The final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge.
AVDD = 5V 1
POWER - mW
AVDD = 3V
0.1
0.01
0
20
40
60
80 100 120 140 THROUGHPUT - kSPS
160
180
200
Figure 15. Power vs. Throughput Rate
CS
t2
SCLK 1 2 3 4
t6
5
tCONVERT
6 11 12 13
B 14 15 16
t3
DOUT THREESTATE ZERO DIN WRITE ZERO ADD1
t4
ADD0 DB11 2 IDENTIFICATION BITS DONTC DONTC ADD1
t7
DB10 DB4 DB3 DB2
t5 t8
DB1 DB0
t11
tQUIET
t9
SEQ1
t10
ADD0 CODING DONTC DONTC DONTC DONTC
THREESTATE
Figure 16. Serial Interface Timing Diagram
tCYCLE 5 s MIN
CS 1 SCLK 16 1 16 1
tQUIET MIN
16
DOUT DIN
VALID DATA POWER-UP
VALID DATA
Figure 17. General Timing Diagram
REV. 0
-17-
AD7923
Writing information to the Control Register takes place on the first 12 falling edges of SCLK in a data transfer, assuming the MSB, i.e., the WRITE bit, has been set to 1. The 16-bit word read from the AD7923 will always contain two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 12-bit conversion result. As outlined in the Operating Modes section, not less than 5 ms should be left between consecutive valid conversions; however there is one case where this does not necessarily mean that at least 5 ms should always be left between CS falling edges. Consider the case when writing to the AD7923 to power it up from shutdown prior to a valid conversion. The user must write to the part to tell it to power up before it can convert successfully. Once the serial write to power up has finished, one may want to perform the conversion as soon as possible and not have to wait an additional 5 ms before bringing CS low for the conversion. In this case, as long as there is a minimum of 5 ms between each valid conversion, only the quiet time between the CS rising edge at the end of the write to power up and the next CS falling edge for a valid conversion needs to be met. Figure 17 illustrates this point. Note that when writing to the AD7923 between these valid conversions, the DOUT line will not be driven during the extra write operation. It is critical that an extra write operation as outlined above is never issued between valid conversions when the AD7923 is executing through a sequence function, because the falling edge of CS in the extra write would move the mux onto the next channel in the sequence. This means when the next valid conversion takes place a channel result would have been missed.
MICROPROCESSOR INTERFACING Writing Between Conversions
AD7923*
TMS320C541*
SCLK DOUT DIN CS VDRIVE
CLKX CLKR DR DT FSX FSR
*ADDITIONAL PINS REMOVED FOR CLARITY
VDD
Figure 18. Interfacing to the TMS320C541
AD7923 to ADSP-21xx
The ADSP-21xx family of DSPs is interfaced directly to the AD7923 without any glue logic required. The VDRIVE pin of the AD7923 takes the same supply voltage as that of the ADSP-218x. This allows the ADC to operate at a higher voltage than the serial interface, i.e., ADSP-218x, if necessary. The SPORT0 Control Register should be set up as follows: TFSW = RFSW = 1, Alternate Framing INVRFS = INVTFS = 1, Active Low Frame Signal DTYPE = 00, Right Justify Data SLEN = 1111, 16-Bit Data-Words ISCLK = 1, Internal Serial Clock TFSR = RFSR = 1, Frame Every Word IRFS = 0 ITFS = 1 The connection diagram is shown in Figure 19. The ADSP-218x has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in Alternate Framing Mode and the SPORT Control Register is set up as described. The frame synchronization signal generated on the TFS is tied to CS and, as with all signal processing applications, equidistant sampling is necessary. However, in this example, the timer interrupt is used to control the sampling rate of the ADC, and under certain conditions equidistant sampling may not be achieved.
AD7923*
ADSP-218x*
The serial interface on the AD7923 allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7923 with some of the more common microcontroller and DSP serial interface protocols.
AD7923 to TMS320C541
The serial interface on the TMS320C541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7923. The CS input allows easy interfacing between the TMS320C541 and the AD7923 without any glue logic required. The serial port of the TMS320C541 is set up to operate in burst mode with internal CLKX0 (Tx serial clock on serial port 0) and FSX0 (Tx frame sync from serial port 0). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The connection diagram is shown in Figure 18. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the TMS320C541 provides equidistant sampling. The VDRIVE pin of the AD7923 takes the same supply voltage as that of the TMS320C541. This allows the ADC to operate at a higher voltage than the serial interface, i.e., TMS320C541, if necessary.
SCLK DOUT CS
SCLK DR RFS TFS
VDRIVE
DIN
DT
*ADDITIONAL PINS REMOVED FOR CLARITY VDD
Figure 19. Interfacing to the ADSP-218x
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AD7923
The Timer Register, for instance, is loaded with a value that will provide an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and therefore the reading of data. The frequency of the serial clock is set in the SCLKDIV Register. When the instruction to transmit with TFS is given (i.e., AX0 = TX0), the state of the SCLK is checked. The DSP will wait until the SCLK has gone high, low, and high before the transmission will start. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data may be transmitted, or it may wait until the next clock edge. For example, if the ADSP-2189 has a 20 MHz crystal such that it has a master clock frequency of 40 MHz, then the master cycle time would be 25 ns. If the SCLKDIV Register is loaded with the value 3, then a SCLK of 5 MHz is obtained, and eight master clock periods will elapse for every SCLK period. Depending on the throughput rate selected, if the Timer Registers are loaded with the value 803, 100.5 SCLKs will occur between interrupts and subsequently between transmit instructions. This situation will result in nonequidistant sampling as the transmit instruction is occurring on a SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, equidistant sampling will be implemented by the DSP.
AD7923 to DSP563xx APPLICATION HINTS Grounding and Layout
The AD7923 has very good immunity to noise on the power supplies as can be seen by the PSRR versus Supply Ripple Frequency plot, TPC 3. However, care should still be taken with regard to grounding and layout. The printed circuit board that houses the AD7923 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. All three AGND pins of the AD7923 should be sunk into the AGND plane. Digital and analog ground planes should be joined at only one place. If the AD7923 is in a system where multiple devices require an AGND to DGND connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7923. Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7923 to avoid noise coupling. The power supply lines to the AD7923 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, like clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 mF tantalum in parallel with 0.1 mF capacitors to AGND. To achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The 0.1 mF capacitors should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), such as the common ceramic types or surfacemount types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.
Evaluating AD7923 Performance
The connection diagram in Figure 20 shows how the AD7923 can be connected to the ESSI (Synchronous Serial Interface) of the DSP563xx family of DSPs from Motorola. Each ESSI (two on board) is operated in Synchronous Mode (SYN bit in CRB = 1) with internally generated word length frame sync for both Tx and Rx (bits FSL1 = 0 and FSL0 = 0 in CRB). Normal operation of the ESSI is selected by making MOD = 0 in the CRB. Set the word length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1 so the frame sync is negative. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the DSP563xx provides equidistant sampling. In the example shown in Figure 20, the serial clock is taken from the ESSI so the SCK0 pin must be set as an output, SCKD = 1. The VDRIVE pin of the AD7923 takes the same supply voltage as does the DSP563xx. This allows the ADC to operate at a higher voltage than the serial interface, i.e., DSP563xx, if necessary.
AD7923*
DSP563xx*
SCLK DOUT DIN VDRIVE CS
SCK SRD STD SC2
*ADDITIONAL PINS REMOVED FOR CLARITY VDD
The recommended layout for the AD7923 is outlined in the evaluation board for the AD7923. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the Eval-Board Controller. The Eval-Board Controller can be used in conjunction with the AD7923 Evaluation Board, as well as many other Analog Devices evaluation boards ending in the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7923. The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7923. The software and documentation are on a CD shipped with the evaluation board.
Figure 20. Interfacing to the DSP563xx
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AD7923
OUTLINE DIMENSIONS 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16)
Dimensions shown in millimeters
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
0.15 0.05
COMPLIANT TO JEDEC STANDARDS MO-153AB
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PRINTED IN U.S.A.
C03086-0-11/02(0)

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